Integrated circuits are formed on wafers by well-known processes and materials. These processes typically include the deposition of thin film layers by sputtering, metal-organic decomposition, chemical vapor deposition, plasma vapor deposition, and other techniques. These layers are processed by a variety of well-known etching technologies and subsequent deposition and polishing steps to provide a completed integrated circuit.
A crucial component of integrated circuits is the wiring or metallization layer that interconnects the individual circuits. Conventional metal deposition techniques include physical vapor deposition, e.g., sputtering and evaporation, and chemical vapor deposition techniques. More recently, integrated circuit and equipment manufacturers have developed electrochemical deposition techniques to deposit primary conductor films on semiconductor substrates.
Wiring layers traditionally contained aluminum and a plurality of other metal layers that are compatible with the aluminum. In 1997, IBM introduced technology that facilitated a transition from aluminum to copper wiring layers. This technology has demanded corresponding changes in process architecture towards damascene and dual damascene architecture, as well as new process technologies.
Conductive layers are typically deposited on a dielectric layer and typically comprise metals such as tantalum (Ta), tungsten (W), titanium (Ti), aluminum (Al), copper (Cu), and alloys thereof, and semiconductors, such as doped silicon (Si), doped polysilicon, and refractory metal silicides. The dielectric layer typically contains openings, or feature cavities, (e.g., vias and trenches) that are filled with conductive material to provide a path through the dielectric layer to previously deposited layers and to circuit devices. After the conductive layer is polished, only the conductive material filling the feature cavities remains in the dielectric layer.
A typical damascene or dual damascene process flow scheme for fabricating copper interconnects, such as copper lines and vias, typically includes: forming a trench pattern on a layer dielectric layer using an etch-resistant photoresist; etching a trench pattern; removing the photoresist; forming a via pattern on a dielectric material using etch resistant photoresist; etching vias; removing resist; depositing a barrier (e.g., tantalum, tantalum nitride, and combination of these) and a copper seed layer (e.g. using plasma vapor deposition, PVD); electroplating copper to fill the etched feature cavities; and polishing copper and barrier off the wafer face leaving copper-filled electrically isolated interconnect circuitry.
As the number of levels in an interconnect technology is increased, the stacking of additional layers produces more rugged and complex topography. Compounding this problem, electroplating bath additives are now commonly utilized to promote rapid “bottom-up” filling of high aspect-ratio features in damascene copper electroplating processes to ensure complete void-free metal fill of high aspect ratio features (features deeper than they are wide). Baths with good “bottom-up” filling characteristics fill high aspect ratio features more rapidly and without creating void or seam when compared to baths with less effective combinations of such additives. While the action of plating bath additives is still a subject or active investigation, it is generally now accepted that bottom-up filling of high aspect ratio features is controlled by the geometrical concentration of a strongly adsorbed plating bath “accelerator” bound within and on the walls of the feature.
As the feature growths, the surface area decreases within the feature and concentrates the adsorbate, lowering the resistance to charge transfer there when compared to the generally flatter field regions of the substrate surface, thereby creating an “acceleration” of the plating rate within the recess region. (See, for example, J. Osterwald and J. Schulz-Harder, Galvanotechnik, 66, 360 (1975); J. Osterwald, Oberfläche-Surface, 17, 89 (1976); J. Reid and S. Mayer, in Advanced Metallization Conference (1999); M. E. Gross, T. Gessner, N. Kobayashi, and Y. Yauda, Editors, p. 53, MRS, Warrendale, Pa. (2000); A. C. West, S. Mayer, and J. Reid, Electrochem. Solid-State Letters, 4, C50 (2001); T. P. Moffat, D. Wheeler, and D. Josell, “Superfilling and the Curvature Enhanced Accelerator Coverage Mechanism”, The Electrochemical Society Interface (Winter 2004). Therefore, baths with good “bottom-up” filling characteristics typically fill smaller (higher aspect ratio) features more rapidly than larger (lower aspect ratio) features. In some cases (e.g., plating baths with superior bottom-up filling characteristics and little or no leveling additives), plating continues at an accelerated rate after completing the small-feature filling stage. When many high-aspect ratio features are located in close proximity, the high degree of adsorbed accelerator originally associated with the high surface area of that region remains after the features have filled. Hence, growth continues at an accelerated rate beyond the point of filled features, and into the period where metal between the features has merged. When this happens, a macroscopic raised area (series of thicker metallized bumps or a raised plateau) forms over the entire region of underlying high aspect ratio features. This bump formation is also termed “feature overplating” or “momentum plating”.
The use of advanced “bottom-up” electrofilling techniques with wafers having low and high aspect-ratio features has created a problem of deposited metal surfaces with a wide range of topography, that is, topography containing a large range of height and width variations in both recessed and raised areas. Commonly, features vary in width by two to three orders of magnitude on a single layer. As a specific example, a 0.5 μm-deep (thick dielectric) level can have feature widths of from 0.1 μm to 100 μm. Therefore, while electroplating is the preferred method of metallization, various aspects of improved plating regimens create challenging topography for subsequent planarization
A principal objective of damascene circuit interconnect fabrication is to create metal isolated by and embedded in a dielectric medium. Modern copper electroplating for damascene processes proceeds by a “bottom up” fill mechanism that preferentially fills high-aspect-ratio features such as deep trenches and vias on a wafer surface. The preferential filling of recessed features requires careful control of process conditions. U.S. Pat. No. 6,946,065, titled “Process for Electroplating Metal into Microscopic Recessed Features”, issued Sep. 20, 2005 to Mayer et. al., which is hereby incorporated by reference for all purposes, teaches techniques for reducing or avoiding the formation of seams and/or voids when electroplating the interior regions of microscopic recessed features. For the most part, prior art processes do not preferentially fill and planarize low-aspect-ratio features and, therefore, they require significant excess metal deposition (“overburden.”) Overburden is the additional copper deposited on the substrate to ensure that all low-aspect-ratio features are completely filled (essentially in an isotropic fashion) to the plane of a base layer, that is, to the plane of the isolating dielectric surface (the “field”). Since the preferential “bottom-up” filling generally does not occur in low-aspect-ratio features, the surface of the overburden above low-aspect-ratio features typically follows the contours of the underlying low-aspect-ratio features. In most cases, the overburden on field regions is slightly thicker than the thickness of the damascene dielectric layer, typically on the order of 1.2 times the depth of the deepest feature. So, for example, a damascene structure that has 0.5 micrometers (μm) deep features typically requires an overburden of at least approximately 0.7 μm to 0.8 μm.
The goal of damascene fabrication operations is to isolate finally the individual lines within the feature cavities of the dielectric layer. Since the filling of low-aspect-ratio features is largely isotropic, plating leads to very little if any reduction in the overall topography of the surface. The step change in plated topography is essentially identical to the initial patterned cavity (recess) depth in the dielectric media. Note that if metal overburden were isotropically removed after filling of low-aspect-ratio feature cavities, then these low-aspect-ratio features would loose metal below the plane of the dielectric (i.e., below the field plane) before the metal over high-aspect-ratio lines and the field-area metal were removed. Various approaches and techniques of plating, planarization and polishing have been developed in the prior art with the goal that metal still completely fills these low-aspect-ratio features after overburden has been removed and the individual metal lines have been isolated. These approaches and techniques generally require overburden.
Overburden is undesirable for a number of reasons. It requires deposition of considerable amounts of excess copper that is essentially wasted. It requires an extra step of removing the overburden material. Thus, overburden represents additional materials costs (excess copper deposited and removed), as well as decreased throughput and productivity. In current processes, overburden is removed by a planarization technique such as chemical mechanical polishing (CMP), electrochemical mechanical polishing (eCMP), or electropolishing. CMP and eCMP are particularly expensive processes that generally use corrosive chemical and slurry formulations on large (wafer scale or larger) pads to polish the surface of the integrated circuit substrate. Such pad-rubbing processes are often difficult to control and the polishing end-point can be difficult to detect. The high equipment cost, waste handling cost, and low throughput contribute to the overall expense of CMP and eCMP. Also, with the introduction of porous low-k dielectrics in semiconductor devices, modification of traditional CMP and even eCMP processes is required, as current methods can crack and/or delaminate low-k materials, which typically have a very low compression strength and extreme fragility. Furthermore, none of these techniques achieve perfect planarization.
Chemical mechanical planarization (CMP) is the most common currently used process used to remove excess material from a surface. It typically includes the use of a polishing pad and a solution containing an abrasive along with passivating agents and/or chemical agents that either retard or assist the planing of the material. CMP may be used for planing portions of wafers comprising dielectrics, such as silicon dioxide, or metals, such as copper, aluminum or tungsten. In copper CMP processes, excess copper is planarized (polished) off the top of the wafer surface to expose the thin pattern lines of copper metal inlaid within the barrier layer or dielectric substrate material. Polishing of the substrate is conducted until the underlying substrate is exposed, a condition commonly referred to as breakthrough. For copper CMP, breakthrough is defined as removal of metal from the top of the substrate until the underlying barrier layer above the dielectric film is first exposed. Breakthrough can be detected by optical reflectance from the substrate, by changes in polishing wheel temperature, by changes in polishing wheel torque, or by changes in chemical composition of used polishing solution.
Once the excess copper is removed by the polishing step, the wafer must be cleaned with additional chemicals and soft pads to remove the abrasive particles that adhere to the wafer.
To create advanced semiconductor devices that contain multiple levels of metal lines in a dielectric requires the use of new dielectric materials. These new dielectric materials are commonly referred to as low-k dielectrics. Compared to traditional silicon dioxide dielectric, the newer low-k dielectrics are softer and less tough. The large downward pressure exerted onto a wafer during typical CMP polishing may damage fragile low-k dielectrics.
Lower pad pressures and stiffer (less compliant) pads are generally useful in achieving better local planarization efficiency and low-k compatibility, but must be balanced with the competing needs of performing the process at an economically viable rate over a large length scale (the width of the wafer). While multilayer laminated pads containing materials of variable compliance (stiffer layer near the interface, more compliant layers further away from the interface) help address some mechanical tolerance requirements, it is well know that CMP and eCMP techniques suffer from substantially non-ideal planarization performance and global non-uniformities. Neither of these techniques achieve perfect planarization in which the thickness of the metal is the same over all features at all locations of the wafer just prior to all metal being “cleared” from the surface field regions between the embeded features. Non-uniformities therefore exist on two levels: The die level (local) and global level. As a result of CMP technology's inability to achieve perfect die-level planarization, and because of global wafer-scale height variations, excess processing (beyond the point where metal over the field around the feature has been completely removed) occurs on certain areas than would otherwise be desirable. Hence, substantial overpolishing over some feature types (typically larger features) and parts of the wafer occurs.
A difficult problem of CMP includes defect generation and scratching of fine-lined metal in dielectric features by foreign particles as well as the agglomerations of abrasive particles. Scratching results in damage to interconnects and reduces device manufacturing yield. A conglomerate of particles and gels can be removed from the slurries using point-of-use filtration prior to substrate polishing; however, plugging of the filters requires interruption of the process for filtrate removal, which is expensive and results in lower production. Conglomerate slurry particles also plug the surface of the polishing pad, and polishing pads must be periodically reconditioned in a non-value-adding step called dressing.
Measures must typically be taken to avoid “dishing” of filled metal features, erosion of field dielectric and metal lines, and undesired propagation of underlying topography during CMP. (See, for example, “Establishing the discipline of physics-based CMP modeling”, S. R. Runnels, and T. Lauren, Solid State Technology, (March 2002). Dishing occurs on the interconnect metal primarily in larger features and in contact pad regions during the later stages of copper CMP. Because electroplating creates variations in thickness over the dielectric, and because underlying topography from lower levels is transferred to higher levels of the dielectric, within-die variations in the amount of metal thickness over the dielectric persist up to the point of the first clearing of interconnect metal over the damascene structure (i.e., barrier exposure). Because neither the metal deposition (e.g., electroplating) nor metal removal (e.g., CMP) processes are perfectly uniform across the wafer surface, global non-uniformities also exist. Dishing of a feature generally occurs when the metal has cleared locally around the periphery of the feature cavity but the polishing process is continued over that feature. This “overpolishing’ is needed because other areas of the surface have not reached the clearing endpoint. A rubbing pad is supported (contacted) at the feature periphery by the barrier film and dielectric, and the barrier material is largely unaffected (i.e., removed at a much slower rate than metal) as the CMP of the surface continues. The problem then arises that the interconnect metal (e.g., copper) in the feature is slowly removed, preferentially in the feature, hence “dished”. It is generally desirable to remove all the interconnect metal (copper) above the barrier/dielectric level from the top of the barrier/dielectric at this point in the process before proceeding with removing the (typically conductive) barrier film. As a result, “overpolishing” is often conducted and dishing occurs.
After interconnect (copper) removal above the field has been completed, the barrier layer is exposed. If metal interconnect removal is properly performed, the barrier remains largely unaffected. During the subsequent CMP of barrier/dielectric material, the risk of erosion arises. Erosion arises from locally varying polishing properties at different areas of the substrate surface. It is believed that variations in mechanical “strength” of the substrate at different points on the circuit cause varying polishing properties. Various feature densities and the different mechanical properties of the metal and dielectric are principal causes of variations in mechanical strength. Removal and polishing of barrier and dielectric material through CMP can be viewed as a much more mechanically driven process than metal CMP. After the barrier has been removed and the dielectric is exposed, the goal of a polishing process is to avoid dishing of embedded metal features and to avoid erosion of high-density feature areas. To eliminate or minimize dishing, some amount of dielectric is typically removed, but this also reduces the thickness of the copper interconnects and increases their electrical resistance. The overall deviations from planarity caused by dishing, erosion, and underlying topography can also lead to difficulties in obtaining good focus across the die during subsequent lithographic steps. More importantly, topography introduced by these effects is replicated at the next metal level, creating “underlying topography”. These areas are particularly troublesome for CMP technology because of the competing requirements of having planarization and compliance. Often CMP has difficulty clearing metal from recessed areas of underlying topography, leaving “puddles” of metal. To remove these puddles, the CMP process is generally continued for a longer period of time than otherwise desirable (because this can create excessive dishing).
Alternatives to CMP include electrolytic etching techniques such as electropolishing or electroless etching. Compared to CMP, these are relatively low cost techniques, do not exhibit a number of CMP related defects (e.g., scratching), and do not require complex post-CMP slurry-particle-removal with brushes, megasonic energy or cleaning chemicals. They also provide much higher processing rates. Electropolishing is a method of polishing metal surfaces by applying an electric current through an electrolytic bath, and removing metal via electrolytic dissolution. In many ways the process may be viewed as the reverse of electroplating. Various electropolishing techniques are known in the art.
While etching (electroless etching), electropolishing, electrochemical etching, and membrane mediated electropolishing processes are simpler, less costly operations than CMP (and eCMP), they generally have a more limited ability to planarize a “contoured” surface over longer planarization lengths (either wider features or over longer distances). In contrast, CMP selectively removes metal from exposed surfaces, but not from recesses. Also, due largely to its use of a pad, CMP can planarize over a much wider range of distances and sizes than alternatives to CMP.
Although many approaches in the prior art address the need for simpler and improved electroplanarization in semiconductor device fabrication, they generally address alternative planarization techniques performed after deposition of an undesirably thick overburden with substantial variations in topography.
Osterwald et al., in “Wirkung von Badzusätzen bei der kathodischen Metallabscheidung”, Galvanotechnik, 66, Nr. 5, pp. 360-365 (1975), Leuze Verlag, Saulgau, Germany, and “Leveling and Roughening by Inhibitors and Catalysts” Oberfläche-Surface, 17, 89, (1976), teach an additive in solution that absorbs onto a cathode surface. The absorbed additive acts as a catalyst of metal deposition conducted with an electroplating solution that does not contain the additive, thereby increasing a metal deposition rate. When the catalyzing additive is absorbed onto a surface having a recess, the surface concentration of catalyzing additive in the recess increases compared to its concentration in non-recessed areas as metal deposition proceeds. As a result, the rate of metal deposition in the recess becomes greater than the metal deposition rate at non-recessed areas. This leads to relative planarization of the deposited metal compared to topography resulting from metal plating on a substrate without adsorbed catalyzing additive. Later, others demonstrated the validity and usefulness of these concepts in interpreting, modeling and controlling preferential filling of small damascene features (see, for example, J. Reid and S. Mayer, in Advance Metallization Conference Proceedings, 1999, p. 53; A. C. West, S. Mayer, and J. Reid, Electrochem. Solid-State Lett., 4, C50, (2001); T. P. Moffat, D. Wheeler, W. H. Huber, and D. Josell, Electrochem Solid State Lett, 4, C26, (2001); and T. P. Moffat, D. Wheeler, and D. Josell, Electrochemical Society Interface, p. 46, (Winter 2004). U.S. patent application Ser. No. 10/739,822, filed Dec. 17, 2003, by Mayer et al., having the title “Method for Planar Electroplating”, teaches a method of selectively attaching a plating accelerator to recessed regions of the dielectric layer before electroplating to achieve selectively accelerated plating (SAP) of metal in the recessed regions.
Electropolishing is a method of polishing metal surfaces by applying an electric current through an electrolytic bath, and removing metal via electrolytic dissolution. Electropolishing may be viewed as the reverse of electroplating. For example, U.S. Pat. No. 5,096,550, issued Mar. 17, 1992, to Mayer et al., which is hereby incorporated by reference, teaches an electropolishing apparatus having a vessel filled with electrolytic solution, a cathode mounted in the vessel, and an anode containing the semiconductor substrate positioned in the vessel. U.S. Pat. No. 5,256,565, issued Oct. 26, 1993, to Bernhardt et al., teaches a method of forming a planarized metal interconnect by connecting a substrate containing a metal-filled trench or via to the anode of a DC voltage source, placing the substrate in an electrolyte, and flowing DC current through the substrate. United States Patent Application Publication No. 2004/0134793, published Jul. 15, 2004, by Uzoh et al., teaches a method and an apparatus for electroetching metal from a substrate surface by applying a voltage between an electrode and a substrate and continuously applying an etching solution to the substrate surface as a plurality of rollers are rotated.
Nevertheless, a problem arises during the electropolishing of surfaces in which a large number of low aspect-ratio (larger width than depth) features exist. Wide interconnect lines (trenches cut in a dielectric layer for a damascene process) and contact/bond pads often have low aspect ratios. Low-aspect-ratio features generally require the plating of an overburden layer slightly thicker than the thickness of the damascene layer so that the feature is completely filled after planarization. The metal fill profile above these features exhibits large recesses having profiles that resemble the original low aspect-ratio feature. The metal processes used to deposit the metal, which are substantially conformal over such low aspect-ratio features, are typically not continued to a point that would geometrically “close” such recesses, because to do so would require depositing a very thick metal layer. Depositing a thick metal layer would be uneconomical due to necessary removal of the large excess of metal at a later stage. Conventional electropolishing techniques can planarize a surface in which the recessed feature to be planarized is no more than perhaps three times as wide as it is deep. For features wider than these, the rate of removal is essentially uniform everywhere. When the metal layer is electropolished to the dielectric surface, recesses over low-aspect-ratio features are propagated and expanded to produce recesses that span the width of these features, leaving effectively little or no metal in the metal pad regions. This is an unacceptable result.
Similar problems may arise from chemical (nonelectrolytic) wet etching of metal from a substrate surface. Wet etching generally proceeds isotropically; that is, there is no selection between etching of metal from peaks and valleys of the substrate surface and etching occurs over the surface at substantially the same rate everywhere. For example, U.S. Pat. No. 5,486,234, issued Jan. 23, 1996, to Controlini et al., which is hereby incorporated by reference, teaches a method of spin-spray etching particularly suited for removing both field metal and metal embedded in a substrate at substantially the same rate by applying a suitable metal etchant onto a spinning wafer. The process etches the metal evenly on the entire surface of the wafer and is useful after the wafer has been electroplated and planarized, for example, by CMP or electropolishing. Because it is an isotropic, a conformal, operation, it requires an initially planar surface to be useful. If not initially planar, differences in metal height between metal over high-aspect-ratio features and metal over low-aspect-ratio features remain and are further propagated. Furthermore, if chemical wet etching were conducted long enough to remove substantially the metal over the field areas and above “overplated” high-aspect-ratio features of a nonplanar substrate, then excessive over-etching of metal and generation of recesses in low-aspect-ratio features would result.
Another class of methods useful in overburden reduction and planarization is referred to as “brush plating” or “planar plating”. These methods generally employ a brush or pad that acts on the surface to achieve smoother deposits during the plating process. As described above and known in the art, so-called bottom-up fill (also referred to as “superfilling”) methods are now commonly used to fill high-aspect-ratio (i.e., deeper than wide) recess features, though a geometric acceleration concentration mechanism similar to that proposed by Ostwald et. al. However, due to their physical and geometrical limitations, these processes are not capable of filling low-aspect-ratio features (e.g., contact pads). Since both of these feature types can exist on every damascene integrated circuit interconnect level, research into potentially low cost “planar plating” methods has been pursued. Various planar plating methods that attempt to modify the otherwise conformal plating behavior over a recessed low-aspect-ratio region by modifying the plating method (bath additives, transport properties, field effects, etc.) have been reported.
U.S. Pat. No. 3,183,176, issued May 11, 1965, and U.S. Pat. No. 3,313,715, issued Apr. 11, 1967, to Schwartz, teach techniques for brush planar electroplating useful in obtaining smooth electrodeposits, in diminishing surface roughness and in preferentially filling recessed small crevices. A hard polymeric rubbing element with definitely-sized holes is rubbed and moved over a surface while the surface is wetted in a plating bath, in some cases, containing organic plating additives. U.S. Pat. No. 3,751,343, issued Aug. 7, 1973, to Macula et al., describes a useful brush plating apparatus and a process in which electrolyte is held in and moves through a surface-rubbing element having an orbital rubbing like motion simultaneously with electrolytic plating. U.S. Pat. No. 3,619,383, issued Nov. 9, 1971, and U.S. Pat. No. 3,749,652, issued Jul. 31, 1973, to Eisner, teach an apparatus and a method of brush plating that use simultaneous plating and abrasion of the surface to improve metal deposition and to reduce roughness and accumulation of undesired metal.
U.S. Pat. No. 6,867,136, issued Mar. 15, 2005, to Basol et al., teaches a method of brush or “mask-pulsed” plating in which one or more additives that enhance plating are contained in an electrolytic plating solution. Generally similar to the brush plating process of Schwartz above (but note that the patents tend to use their own coined terms for the process, including “mask pulse” plating, “electrochemical mechanical deposition” or ECMD for this technique), the method involves sweeping the top surface of the substrate (field regions) by a brush or pad that contains holes (hence a “mask”). It is known that the use of a rubbing element, such as a pad, in continuous moving contact with a surface such as a wafer creates problems (e.g., defects, feature damage, plating protrusions, metal particle deposition on the pad, and contamination of deposited metal by pad material), and the influence of adsorption dynamics (diffusion, surface reaction rates, local consumption rates, etc.) can make process control difficult. Furthermore, plating selectivity between recessed and exposed regions is generally less than optimal because a finite rate of additive re-adsorption tends to reduce the plating selectivity. The mechanism of masked plating, and specifically the role of a mask-plating pad in creating differential plating activity, remains unclear and leads to doubt regarding optimization, a method's robustness, and its overall utility. Understanding a plating mechanism impacts the ability to design better processes and tool implementation strategies. In addition, while the desired properties of pads have not been specified clearly, the effects of continual contact of a pad with the substrate surface and of the associated continual wear require significant pad conditioning to maintain performance and selectivity. This substantially limits the overall pad life and process flexibility. Replacement of the mask plating pad is not only potentially costly from a material standpoint, but also from a tool utilization and uptime standpoint.
There exists a need for improved technology for depositing and planarizing conductive layers embedded in dielectric substrates having various feature sizes, particularly having both very narrow (submicron) and very wide (on the order of 100 μm) feature widths. Similarly, there exists a need in the semiconductor industry to planarize thin metal films and fine metal interconnect lines inlaid on a patterned substrate that includes dielectric and barrier layer materials. The metal films and interconnect lines and patterns should be substantially free from scratches, dishing and erosion. Techniques for depositing, planarizing and polishing fine copper (or other metal) interconnect lines and metal films on a patterned substrate should yield smooth, undamaged surfaces and have a high throughput rate. Thus, electroplating processes that deposit copper with reduced overburden, that reduce variations in topography, and that improve planarity are highly desirable.